Low-Power RTL Design of AMBA AHB Protocol with Multi-Slave Power Management
DOI:
https://doi.org/10.15662/IJEETR.2026.0802118Keywords:
Low-power RTL design, AMBA AHB protocol, multi-slave architecture, power management techniques, clock gating, dynamic power reduction, bus arbitrationAbstract
The increasing demand for energy-efficient System-on-Chip (SoC) architectures has made power optimization a critical design constraint in modern digital systems. The Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) protocol is widely adopted for high-speed communication between processing elements and peripherals. However, continuous clock activity across AHB components leads to significant dynamic power consumption, especially during idle or low-utilization states
This work proposes a low-power implementation of the AMBA AHB protocol using a clock gating technique to minimize unnecessary switching activity. The proposed architecture introduces selective clock control across major AHB components, including the master, slave, and arbiter modules. By dynamically enabling and disabling the clock based on transaction activity, the system effectively reduces dynamic power without compromising protocol functionality
The design is modeled using SystemVerilog and verified through simulation using industry-standard tools. The experimental analysis demonstrates a considerable reduction in switching activity and overall dynamic power consumption compared to conventional AHB implementations. The results validate that clock gating provides an efficient and scalable solution for low-power SoC design
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