FPGA Implementation of 3-Bit Flash ADC Digital Encoder using Verilog
DOI:
https://doi.org/10.15662/IJEETR.2026.0802149Keywords:
Flash ADC, FPGA, Verilog HDL, Digital Encoder, Thermometer Code, Priority Encoder, 3-Bit ADC, RTL Design, FPGA Synthesis, High-Speed Data ConversionAbstract
This paper presents the FPGA implementation of a 3-bit Flash Analog-to-Digital Converter (ADC) digital encoder using Verilog Hardware Description Language (HDL). The Flash ADC is the fastest ADC architecture, converting analog signals to digital codes in a single clock cycle using parallel comparators. In this work, the digital encoder block of the 3-bit Flash ADC — specifically the thermometer-to-binary priority encoder — is designed, simulated, synthesized, and implemented on an FPGA platform. The encoder accepts a 7-bit thermometer code from the comparator array and converts it into a 3-bit binary output. The Verilog RTL design is verified through functional simulation using a testbench, followed by synthesis and place-and-route on the target FPGA device. Results confirm correct logic operation, low propagation delay, and minimal LUT utilization, demonstrating the suitability of FPGA- based Flash ADC encoder design for high-speed real-time applications such as radar, digital oscilloscopes, and software- defined radio.
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