Design of Low Power Modified Retiming LFSR Architecture
DOI:
https://doi.org/10.15662/IJEETR.2026.0802308Keywords:
LSBsteganography, Built-in self-test (BIST), linear feedback shift register (LFSR)Abstract
LFSR based PN Sequence Generator technique is used for various Steganography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on anyhardware for getting better efficient result. Here we propose Filter structure for parallel LFSR architecture and we also introduce pipelining and retiming technique to increase the speed of LFSR. In order to reduce power consumption in a digital system a set of strategies termed dynamic power management (DPM) is often used. The DPMs strategy consists in disabling the logic circuits that are not performing functional operations during a particular time frame, thus reducing power consumption. Steganography is the art of hiding information in a cover medium such that the existence of information is concealed. An image is a suitable cover medium for steganography because of its great amount of redundant spaces. One simple method of image steganography is the replacement of the least significant bit (LSB) of a cover image with a message bit. Therefore, a new LSB algorithm is proposed here which can effectively resist statistical analysis. In this novel algorithm, every two sample’s LSB bits are combined using addition modulo 2 which is compared to the secret message. Built In Self-Test(BIST) application can run on steganography design, where parallel LFSR is the main module.
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