Fixed-Latency, Multi-Gigabit Serial Links on FPGA using Serdes. International Journal of Engineering & Extended Technologies Research (IJEETR), [S. l.], v. 8, n. 2, p. 3048–3058, 2026. DOI: 10.15662/IJEETR.2026.0802304. Disponível em: https://ijeetr.com/index.php/ijeetr/article/view/726. Acesso em: 25 apr. 2026.